1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a memory, and a circuit design apparatus for designing the circuit of the semiconductor integrated circuit.
2. Description of Related Art
A conventional semiconductor integrated circuit usually places its logic circuit composed of logic cells in a logic region.
In contrast, it places a memory for storing data input to or output from the logic circuit in a hard macro cell region, because the memory is a hard macro with its layout structure as well as its circuit configuration being specified.
Accordingly, the memory is not always placed near the logic circuit, and hence long wiring can be required between the logic circuit and memory in some cases. Thus, it is necessary for the memory to have driving power to cope with the long wiring.
In addition, as for a small capacity memory embedded in a semiconductor integrated circuit, the region for the address decoder and IO buffers corresponding to the memory becomes relatively large when the memory is configured by the hard macro. This is because the hard macro specifies not only the circuit configuration, but also its layout in advance. Furthermore, a ratio of the region including no circuit components becomes relatively large. Accordingly, the area per memory capacity increases with the reduction in the capacity.
If the geometry of the memory with a desired capacity does not match the geometry of the region where the memory is to be placed, a method is applicable of dividing the memory in order to place the subdivisions to the region as disclosed in the following Relevant Reference 1. However, the method configures the memory not with the logic cells, but with the hard macro.
Relevant Reference 1: Japanese patent application laid-open No. 2001-345384 (pages 6 and 7, and FIG. 2).
With the foregoing configuration, the conventional semiconductor integrated circuit has a problem of increasing its area and power consumption because of the long wiring between the logic circuit and the memory. In addition, it has a problem of increasing the ratio of the region where no circuit component is formed, when a small capacity memory is embedded in the circuit.
Furthermore, it has a problem of requiring a lot of time and manpower when the memory is configured with the hard macro because of a difficult circuit design.